Japanese Laid-Open Patent Publication No. 2003-318398 discloses a semiconductor device. In such a device, an N−-type polycrystal silicon region and an N+-type polycrystal silicon region are formed and adjoined to a main surface of a semiconductor substrate, in which an N−-type silicon carbide epitaxial region is formed on an N+-type silicon carbide substrate. The N−-type silicon carbide epitaxial region, the N−-type polycrystal silicon region and the N+-type polycrystal silicon region form a heterojunction. Further, a gate electrode is formed adjacent to a junction portion of the N−-type silicon carbide epitaxial region and the N+-type polycrystal silicon region via a gate insulation film. The N−-type polycrystal silicon region is connected to a source electrode and a drain electrode is formed on another surface of the N+-type silicon carbide substrate.